Legacy Course Catalog
ECE 670 - Modeling And Optimization Of High-Performance Interconnects
| Effectivity: | 05/19/2003 - Fall 2007 *** @ Purdue West Lafayette Traditional |
|---|---|
| Credits: | 3 |
| Instructional Types: | Lec |
| Usually Offered: | fal |
| Short Title: | Mdl&Opt High-Perf Intr |
| Description: | RLC extraction of VLSI interconnects. Modeling of interconnects as RLC trees or networks. Elmore delay model. Reduced-order modeling: moment matching, Pade approximation, and Krylov-subspace methods. Device modeling with consideration of resistive shielding in the interconnection load. Delay calculation with consideration of devices and interconnects. Repeater insertion and planning at floorplanning. Timing-driven placement: zero-slack algorithm for delay budgeting, net-based placement, and path-based placement. High-performance clock synthesis: zero-skew routing, bounded-skew routing, and useful-skew routing. Term projects investigating interconnect-related issues are assigned. Prerequisite: ECE 55900, 60800. |
| School: | School Of Electrical And Computer Engineering |
| Department: | Electrical & Computer Engineering |
| Credit By Exam: | NO |
| Repeatable Flag: | NO |
| Temporary Flag: | NO |
| Full Time Privilege Flag: | NO |
| Honors Flag: | NO |
| Variable Title Flag: | NO |
Fall 2007 *** indicates the course was still an active course and was transferred to the Banner Catalog effective Spring 2008. This course was not expired Fall 2007.
